Computer systems often have multiple memory channels that each control an associated DRAM memory bank. In order to improve memory access performance, various surfaces (e.g., frame buffer, texture, etc.) are distributed among the multiple memory channels. Distributing the surfaces among the multiple memory channels is often referred to as memory tiling. When rendering (e.g., drawing) an image, the surface is typically configured to distribute pixels within a scan line evenly across all memory channels. As such, during display scan-out, a display controller must make read requests from all memory channels to scan-out each line.
When the system is not actively used, a display displays the same image over and over again (commonly referred to as a static screen state or a user away state). When in the static screen state, the display data can be compressed to minimize the power consumption. However, even with compression, all of the channels are required and can only enter a lower power mode for a short time between requests from the display for the display data. Furthermore, modern DRAM devices, such as GDDR5 for example, require more time to transition from a low power mode—making it nearly impossible for the channels to enter low power modes between memory requests. As such, known systems can consume a considerable amount power.
One way to overcome the aforementioned drawback is to avoid using certain DRAMs (e.g., GDDR5) that require longer wake up times. When using DRAMs with shorter wake up times (e.g., DDR2/3, GDDR2/3), all memory channels can be turned on and several lines worth of image data can burst into an internal buffer of a GPU. Once the data is in the internal buffer, all the memory channels can enter a low power mode until the internal buffer has exhausted the data. This is often referred to as a display stutter mode. However, due to the longer wakeup times of modern DRAMs (e.g., GDDR5), this solution is not practical.
Accordingly, a need exists for a circuit and method to reduce power consumption of systems using memory tiling while overcoming the aforementioned disadvantages of conventional circuits and methods.